The invention relates to forming features of a semiconductor device, and more particularly to formation of trenches.
In the process of forming semiconductor devices, the devices are generally tested in a number of ways. Typically, an integrated circuit design is configured into a blueprint which is copied by complex machinery into a physical structure. After fabrication, the physical structure enters a debug cycle. During debug, the integrated circuit product is tested to identify and correct any logical or speed test issues. Debug laboratory tools are designed to reduce the debug cycle times.
One such debug tool is a focused ion beam (FIB) tool which may be used for circuit editing, circuit debug, fault isolation, and failure analysis. One task performed by a FIB tool is formation of device features, such as a trench. Such a trench may be formed on a backside of a wafer so that underlying layers of the integrated circuit may be edited. Typically, such a trench is fabricated by forming a small series of box patterns (typically five or less), each manually defined by a user at the same location with progressively smaller sizes, each having an etch depth of ⅕ (or more) of the intended total depth. However such a trench has an undesirable stair step pattern and a sharp edge pattern. This pattern leads to increased resistance, capacitance, lower frequency transmission and voids of a metal line formed in the trench, among other problems. Thus a need exists to form features to reduce or avoid such problems.